The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2007
Filed:
Jun. 28, 2002
Brian Geoffrey Lucas, Barrington, IL (US);
Philip E. May, Palatine, IL (US);
Kent Donald Moat, Winfield, IL (US);
Raymond B. Essick, Iv, Glen Ellyn, IL (US);
Silviu Chiricescu, Chicago, IL (US);
James M. Norris, Naperville, IL (US);
Michael Allen Schuette, Wilmette, IL (US);
Ali Saidi, Cambridge, MA (US);
Brian Geoffrey Lucas, Barrington, IL (US);
Philip E. May, Palatine, IL (US);
Kent Donald Moat, Winfield, IL (US);
Raymond B. Essick, IV, Glen Ellyn, IL (US);
Silviu Chiricescu, Chicago, IL (US);
James M. Norris, Naperville, IL (US);
Michael Allen Schuette, Wilmette, IL (US);
Ali Saidi, Cambridge, MA (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A re-configurable, streaming vector processor () is provided which includes a number of function units (), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch () and a micro-sequencer (). The re-configurable interconnection switch () includes one or more links, each link operable to couple an output of a function unit () to an input of a function unit () as directed by the micro-sequencer (). The vector processor may also include one or more input-stream units () for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface () to the host processor. The vector processor also includes one or more output-stream units () for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.