The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2007

Filed:

Sep. 27, 2002
Applicants:

Vijay Kumar Pathak, San Jose, CA (US);

Bharadwaj Parthasarathy, Plano, TX (US);

Srinath Devalapalli, Sachse, TX (US);

Inventors:

Vijay Kumar Pathak, San Jose, CA (US);

Bharadwaj Parthasarathy, Plano, TX (US);

Srinath Devalapalli, Sachse, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 10/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.


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