Semiconductor memory storage device and its control method

Abstract

A redundancy judge circuit () includes a redundancy judge circuit address+1 controller (), an even-numbered redundant address judge section (), an odd-numbered redundancy judge section (), a redundant address ROM (), a redundant IOROM (), and a select section (). The redundancy judge circuit () may also include a memory cell circuit (), a read circuit (), and an address generator circuit (). With this structure, redundancy remedy can be conducted even during the burst operation due to the 2-bit prefetch, and slowing of the read operation speed can be prevented. Because it is possible to reduce the signal bus length of a decode signal bus in a column direction to substantially half and to reduce a decode signal bus region to substantially half, it is possible to prevent the wiring density in the wiring region of the decode signal bus from becoming high thereby preventing an increase in the read speed.