The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2006
Filed:
Mar. 08, 2005
Masashi Yamawaki, Kasugai, JP;
Masashi Yamawaki, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A delay circuit is constructed by connecting taps TAP–n for providing with a unit delay time (τ) in series on multiple stages. Each tap has the same configuration and an objective signal is inputted to a signal input terminal IN. The output terminal of a preceding stage tap is connected to a between-stages connecting terminal IN. An output terminal O is connected to the between-stages connecting terminal of a next stage tap. The signal input terminal and the between-stages connecting terminal are connected to one input terminal of NAND gatesand a tap selection signal is inputted to the other input terminal. The output terminal is connected to a NAND gate. One of the NAND gatesfunctions as a logical inversion gate corresponding to a tap selection signal so as to enable propagation of the signal. At this time, in the other NAND gate, the output signal is fixed to high level and the NAND gatealso functions as a logical inversion gate. The objective signal is propagated by the NAND gatesand the preceding stage signal is propagated by the NAND gates. By constructing the NAND gateswith the same structure, the unit delay time (τ) can be matched accurately.