Dual mode voltage controlled oscillator having controllable bias modes and power consumption

Abstract

Disclosed is an oscillator circuit () for use in a local oscillator of an RF communications device () that communicates over an RF channel. The oscillator circuit includes an oscillator transistor coupled to a power supply voltage (Vcc) through a buffer transistor, and a biasing network having bias voltage outputs coupled to a control input of the oscillator transistor and to a control input of the buffer transistor. In one embodiment the bias voltage network is coupled to Vcc, while in another embodiment the bias voltage network is coupled to a separate voltage (Vbias). Circuitry is provided for setting a magnitude of Vcc and/or Vbias as a function of at least one of RF channel conditions, such as channels conditions determined from a calculation of the (SNR), or an operational mode of the RF communications device. The magnitude of Vcc (and Vbias) may be set between about zero volts (i.e., turned off) and some maximum value. The operational mode can be, for example, one of a TDMA, burst-type narrow bandwidth mode, or a CDMA, substantially continuous, wider bandwidth mode. The value of Vcc and/or Vbias maybe set so as to minimize power consumption as a function of an amount of allowable local oscillator phase noise. A broad bandwidth/narrow bandwidth dual mode RF transceiver in accordance with these teachings includes at least one phase locked loop (PLL) that includes a voltage controlled oscillator (VCO) providing a local oscillator signal for at least one of an I/Q modulator or an I/Q demodulator; a processor responsive to an output of said I/Q demodulator for determining at least one aspect of RF channel quality; and circuitry coupled between the processor and the VCO for minimizing at least VCO power consumption as a function of an amount of allowable VCO phase noise for a current RF channel quality.