The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7151228 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 19, 2006

Filed:

Jan. 29, 2002
Applicants:

Yoshihisa Takase, Higashiosaka, JP;

Tsuneshi Nakamura, Hirakata, JP;

Inventors:

Yoshihisa Takase, Higashiosaka, JP;

Tsuneshi Nakamura, Hirakata, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention comprises a plurality of laminating double-side circuit boards and a plurality sheets of prepreg for interlayer connection that are placed one on another. Via holes extend from the circuit on one side of each laminating double-side circuit board to the circuit on the other side thereof. Each via hole is filled with electro-conductive material to connect the circuits on both sides of the laminating double-side circuit board. The pad on a laminating double-side circuit board and the pad on another laminating double-side circuit board are laminated via a sheet of prepreg for interlayer connection so that the respective pads are opposed to each other via the through hole filled with electro-conductive material formed through the sheet of prepreg for interlayer connection. Thereby, the respective pads on the laminating double-side wiring circuit boards are electrically connected with one another. Thus, the present invention can provide a multilayer printed wiring board having shorter production time, excellent reliability, and high yield.


Find Patent Forward Citations

Takase, Yoshihisa. (2006). Laminating double-side circuit board, manufacturing method thereof, and multilayer printed circuit board using same (U.S. Patent No. 7151228). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7151228

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