The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2006

Filed:

Jun. 05, 2003
Applicants:

Haim Goldberger, Mediin, IL;

Sik Lui, Sunnyvale, CA (US);

Jacek Korec, San Jose, CA (US);

Y. Mohammed Kasem, Santa Clara, CA (US);

Harianto Wong, Santa Clara, CA (US);

Jack Van Den Heuvel, Los Gatos, CA (US);

Inventors:

Haim Goldberger, Mediin, IL;

Sik Lui, Sunnyvale, CA (US);

Jacek Korec, San Jose, CA (US);

Y. Mohammed Kasem, Santa Clara, CA (US);

Harianto Wong, Santa Clara, CA (US);

Jack Van Den Heuvel, Los Gatos, CA (US);

Assignee:

Vishay-Siliconix, Santa,Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.


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