The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2006

Filed:

Mar. 17, 2003
Applicants:

Kazuo Itabashi, Kawasaki, JP;

Osamu Tsuboi, Kawasaki, JP;

Yuji Yokoyama, Kawasaki, JP;

Kenichi Inoue, Kawasaki, JP;

Koichi Hashimoto, Kawasaki, JP;

Wataru Futo, Kawasaki, JP;

Inventors:

Kazuo Itabashi, Kawasaki, JP;

Osamu Tsuboi, Kawasaki, JP;

Yuji Yokoyama, Kawasaki, JP;

Kenichi Inoue, Kawasaki, JP;

Koichi Hashimoto, Kawasaki, JP;

Wataru Futo, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01O 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.


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