The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
Sep. 26, 2003
Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths
Kazi Asaduzzaman, Milpitas, CA (US);
Wilson Wong, San Francisco, CA (US);
Sergey Shumarayev, San Leandro, CA (US);
Kazi Asaduzzaman, Milpitas, CA (US);
Wilson Wong, San Francisco, CA (US);
Sergey Shumarayev, San Leandro, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.