The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
May. 30, 2000
Supamas Sirichotiyakul, Austin, TX (US);
David T. Blaauw, Austin, TX (US);
Timothy J. Edwards, Austin, TX (US);
Chanhee OH, Cibolo, TX (US);
Rajendran V. Panda, Round Rock, TX (US);
Judah L. Adelman, Shimshon, IL;
David Moshe, Haifa, IL;
Abhijit Dharchoudhury, Austin, TX (US);
Supamas Sirichotiyakul, Austin, TX (US);
David T. Blaauw, Austin, TX (US);
Timothy J. Edwards, Austin, TX (US);
Chanhee Oh, Cibolo, TX (US);
Rajendran V. Panda, Round Rock, TX (US);
Judah L. Adelman, Shimshon, IL;
David Moshe, Haifa, IL;
Abhijit Dharchoudhury, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of improving performance of a dual Vintegrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.