The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
Nov. 01, 2005
Byoung Hwa Lee, Kyungki-do, KR;
Hiroki Sato, Kyungki-do, KR;
Chang Hoon Shim, Kyungki-do, KR;
Sang Soo Park, Kyungki-do, KR;
Hae Suk Chung, Seoul, KR;
Dong Seok Park, Seoul, KR;
Min Cheol Park, Kyunki-do, KR;
Hyun Ju Yi, Seoul, KR;
Min Kyoung Kwon, Kyungki-do, TW;
Seung Heon Han, Seoul, KR;
Byoung Hwa Lee, Kyungki-do, KR;
Hiroki Sato, Kyungki-do, KR;
Chang Hoon Shim, Kyungki-do, KR;
Sang Soo Park, Kyungki-do, KR;
Hae Suk Chung, Seoul, KR;
Dong Seok Park, Seoul, KR;
Min Cheol Park, Kyunki-do, KR;
Hyun Ju Yi, Seoul, KR;
Min Kyoung Kwon, Kyungki-do, TW;
Seung Heon Han, Seoul, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.