The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2006

Filed:

Aug. 13, 2004
Applicants:

James P. Ross, Lakeville, MN (US);

Michael J. Gaboury, Burnsville, MN (US);

Inventors:

James P. Ross, Lakeville, MN (US);

Michael J. Gaboury, Burnsville, MN (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit ('IC') includes a phase-locked loop ('PLL') with a controllable oscillator embedded in the integrated circuit. A phase-lock circuit provides a lock control signal to the controllable oscillator; and a digital-to-analog converter (“DAC”) provides an oscillator adjustment signal to the controllable oscillator according to a digital code. The digital code is generated by an adjustment circuit configured in the fabric of a programmable logic device, or embedded in the IC, for example. In a particular embodiment, the DAC adjusts the PLL to reduce differential mode voltage in the phase-lock circuit.


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Ross, James. (2006). Integrated circuit with digitally controlled phase-locked loop (U.S. Patent No. 7148758). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7148758

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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