The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
Jan. 18, 2005
Bruce L. Inn, San Jose, CA (US);
Ioan Stoichita, Campbell, CA (US);
Bruce L. Inn, San Jose, CA (US);
Ioan Stoichita, Campbell, CA (US);
Micrel, Inc., San Jose, CA (US);
Abstract
A dual mode regulator, having a high current PWM regulator mode and a low current LDO regulator mode, briefly changes the operating parameters of the PWM and LDO regulators during a transition between modes. Changes during the transition period include: raising the error amplifier reference voltage of the LDO or PWM regulator to ensure a definite handover, raising the bias current in the LDO stages during the transition to cause the LDO regulator to quickly and stably respond to voltage glitches, and augmenting the LDO regulator series pass transistors with one or more additional pass transistors during the transition to enable the LDO regulator to handle higher currents. After the transition, the operating parameters of the enabled regulator portion are reset to their nominal values. The PWM regulator is started with a soft start routine to limit current through the power transistor. If the PWM regulator uses a synchronous rectifier, a reverse current limiting circuit is preferably used to limit reverse current when the PWM regulator is starting up to avoid loading down the LDO regulator.