The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7148135 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 12, 2006

Filed:

Apr. 02, 2004
Applicants:

Mitsutoshi Fujita, Osaka, JP;

Shuji Kondo, Ibaraki, JP;

Inventors:

Mitsutoshi Fujita, Osaka, JP;

Shuji Kondo, Ibaraki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A branching point on a wire is detected in the layout results S. A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point Sand that of the route without a dummy buffer being inserted are then calculated S. Based on the delay amounts, an insertion point at which a load-dividing buffer is to be inserted is determined S. On condition that a load-dividing buffer is to be inserted at the insertion point, the drive capability of a driving cell preceding the insertion point is calculated so that timing constraints are satisfied S. Then, after it is confirmed that a load-dividing buffer is insertable at the determined insertion point S, processes of placing a load-dividing buffer, changing the drive capability of the driving cell, and changing wiring information are performed on the layout results S


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Fujita, Mitsutoshi. (2006). Method of designing low-power semiconductor integrated circuit (U.S. Patent No. 7148135). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7148135

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