Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof

Abstract

A method of modifying data of functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell comprises: (a) determining a test case failure in the logic unit through scan chain testing thereof; (b) suspending clocked operations of the logic unit; (c) during suspended clocked operations of the logic unit, performing the following steps: (i) reading logic states of the functional latches; and (ii) modifying the logic state of at least one of the functional latches based on the determined test case failure; (d) restarting clocked operations of the logic unit; and (e) reading logic states of the functional latches resulting from the modification to verify the test case failure of a suspected cell.