The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2006

Filed:

Feb. 08, 2002
Applicant:

Thomas Bolt, Encinitas, CA (US);

Inventor:

Thomas Bolt, Encinitas, CA (US);

Assignee:

Quantum Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of connecting and operating three or more devices to an IDE bus under the conditions that: (1) no more than two IDE devices may be active at any given time on the same IDE bus, and (2) cable/trace lengths for the IDE bus may not exceed the limits set forth in the IDE bus standard. The IDE devices are configured for cable select connected to the IDE bus, wherein no more than two of the IDE devices are powered on at any given. Further, those IDE devices which are powered on at a give time, have the appropriate logic level asserted on CSEL line so that only one IDE device powered on at any time is a 'Master' device, and only one IDE device powered on is a 'Slave'.


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