The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2006

Filed:

Nov. 07, 2003
Applicants:

David Mark, San Jose, CA (US);

Yuezhen Fan, San Jose, CA (US);

Zhi-min Ling, Cupertino, CA (US);

Xiao-yu LI, Palo Alto, CA (US);

Inventors:

David Mark, San Jose, CA (US);

Yuezhen Fan, San Jose, CA (US);

Zhi-Min Ling, Cupertino, CA (US);

Xiao-Yu Li, Palo Alto, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/08 (2006.01); G01R 31/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.


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