The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7145250 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 05, 2006

Filed:

Apr. 25, 2005
Applicants:

Shigeyuki Maruyama, Kawasaki, JP;

Toru Nishino, Kawasaki, JP;

Kazuhiro Tashiro, Kawasaki, JP;

Inventors:

Shigeyuki Maruyama, Kawasaki, JP;

Toru Nishino, Kawasaki, JP;

Kazuhiro Tashiro, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

An LSI package comprises an LSI element and a wiring board. The plurality of pin terminals of the LSI element each includes a first conductive layer and a second conductive layer superposed on the first conductive layer. The plurality of pin terminals of the wiring board each includes a third conductive layer joined to the second conductive layer, and the wiring board further comprises outer joining terminals. The first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer. The LSI element is tested using the outer joining terminals of the wiring board. The second conductive layer and third conductive layer are joined to attain a metallic bond through aggregation derived from pressure, and are reliably brought into electrical contact with each other for a test. After the test is completed, the terminals of the LSI element are peeled off from the terminals of the wiring board. At this time, the second conductive layer is transferred to the third conductive layer, and the first conductive layer is left intact in each of the terminals of the LSI element. The LSI element is then mounted on another wiring board.


Find Patent Forward Citations

Maruyama, Shigeyuki. (2006). Lsi package, lsi element testing method, and semiconductor device manufacturing method (U.S. Patent No. 7145250). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7145250

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