The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2006
Filed:
Apr. 15, 2005
Charvaka Duvvury, Plano, TX (US);
Gianluca Boselli, Richardson, TX (US);
John E. Kunz, Jr., Allen, TX (US);
Charvaka Duvvury, Plano, TX (US);
Gianluca Boselli, Richardson, TX (US);
John E. Kunz, Jr., Allen, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well. Further a finger-shaped diode () with its cathode () located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall ().