The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2006
Filed:
Sep. 02, 2004
Chih-yu Peng, Hsinchu, TW;
Wei-chuan Lin, Taipei, TW;
Chian-chih Hsiao, Taipei Hsien, TW;
Ta-ko Chuang, Taichung, TW;
Chun-hung Chu, Feng Yuan, TW;
Chih-lung Lin, Taichung, TW;
Chin-mao Lin, Chiayi, TW;
Chih-Yu Peng, Hsinchu, TW;
Wei-Chuan Lin, Taipei, TW;
Chian-Chih Hsiao, Taipei Hsien, TW;
Ta-Ko Chuang, Taichung, TW;
Chun-Hung Chu, Feng Yuan, TW;
Chih-Lung Lin, Taichung, TW;
Chin-Mao Lin, Chiayi, TW;
Hannstar Display Corporation, Taipei, TW;
Abstract
A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.