The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2006

Filed:

Oct. 27, 2004
Applicants:

Mitchell T. Lien, Gilbert, AZ (US);

Mark A. Durlam, Chandler, AZ (US);

Thomas V. Meixner, Gilbert, AZ (US);

Loren J. Wise, Tempe, AZ (US);

Inventors:

Mitchell T. Lien, Gilbert, AZ (US);

Mark A. Durlam, Chandler, AZ (US);

Thomas V. Meixner, Gilbert, AZ (US);

Loren J. Wise, Tempe, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.


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