The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Aug. 07, 2001
Friedrich Hapke, Winsen/Luhe, DE;
Friedrich Hapke, Winsen/Luhe, DE;
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
In an arrangement for testing an integrated circuit comprising a combinational logic system, which arrangement performs a test of the behavior of the combinational logic system in comparison with test software which emulates the nominal behavior of the integrated circuit, the signal edge behavior of the combination logic system is checked in that that the test software comprises two identical software models of the combinational logic system to be tested, in which a test sample is applied for test purposes to a first of these software models and whose output signals are coupled to a second of these software models, in that the integrated circuit comprises a test circuit which, in a test mode, applies a first test sample in a first test clock cycle to the input of the combinational logic system of the integrated circuit and takes over the output signal in a buffer memory and which feeds back this output signal as a second test sample in a second test clock cycle to the input of the combinational logic system and again takes over the output signal of the combinational logic system in the buffer memory, and in that at the end of the second test clock cycle, the arrangement compares the results of the combinational logic system of the integrated circuit in the buffer memory with the results of the second software model.