The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Dec. 17, 2003
Shoujun Wang, Nepean, CA;
Haitao Mei, Kanata, CA;
Bill Bereza, Nepean, CA;
Mashkoor Baig, Ottawa, CA;
Tad Kwasniewski, Ottawa, CA;
Shoujun Wang, Nepean, CA;
Haitao Mei, Kanata, CA;
Bill Bereza, Nepean, CA;
Mashkoor Baig, Ottawa, CA;
Tad Kwasniewski, Ottawa, CA;
Altera Corporation, San Jose, CA (US);
Abstract
A recovered clock signal is aligned ('eye centered') with a data signal from which it is recovered by intentionally varying one of the factors or parameters that causes misalignment. For example, if a loop circuit (i.e., a phase-locked loop or a delay-locked loop) is used to recover the clock signal, charge pump current mismatch in the charge pump of the loop circuit is normally one factor in clock-data misalignment, and is also a parameter that can be manipulated. During a test mode, the current mismatch can be varied to obtain the best error rate, which signifies the best clock-data alignment. The test mode can be implemented using built-in self-test circuitry already on the device to transmit test data and then to receive it and analyze it for errors.