The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Dec. 30, 2003
System and method for integrating subcircuit models in an integrated power grid analysis environment
Applicants:
Yong Wang, Fort Collins, CO (US);
Mark Frank, Longmont, CO (US);
Jerimy Nelson, Fort Collins, CO (US);
Inventors:
Yong Wang, Fort Collins, CO (US);
Mark Frank, Longmont, CO (US);
Jerimy Nelson, Fort Collins, CO (US);
Assignee:
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A system and method for integrating a plurality of subcircuit grids in a simulation environment. Upon obtaining a subcircuit layer of a particular granularity for each logical component of an electrical entity (e.g., a semiconductor die in a package and board environment), the nodes of a first subcircuit layer are interconnected to the nodes of a second subcircuit layer using a constraint-based search process.