Input signal receiving device of semiconductor memory unit

Abstract

A receiving device which may include a plurality of pre-amplifiers and a plurality of samplers. Each of the plurality of samplers is connected to the output ports of a corresponding pre-amplifier. Each sampler samples data signals input thereto in response to a corresponding clock signal. The receiving device of a semiconductor memory unit may reduce input capacitance seen from the outside of chip and eliminate mutual interference of signals so as to prevent errors from being generated when data is extracted in the event of over sampling using pre-amplifiers. Furthermore, the receiving device can separately control the pre-amplifier for samplers that receive clock signals for data alignment and the pre-amplifier for samplers that accept clock signals for repeated data reception.