The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Jan. 26, 2004
Chris Speyer, Austin, TX (US);
Chris Speyer, Austin, TX (US);
Legerity Inc., Austin, TX (US);
Abstract
The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting substrate, forming a second layer of epitaxial silicon above the first layer of epitaxial silicon, forming a third layer of epitaxial silicon above the second layer of epitaxial silicon, forming a trench isolation region that extends through at least the third layer of epitaxial silicon and forming a portion of a semiconductor device above the third layer of epitaxial silicon within an area defined by the isolation region. In one illustrative embodiment, the device comprises a substrate, a first layer of epitaxial silicon formed above the substrate, a second layer of epitaxial silicon formed above the first layer of epitaxial silicon, a third layer of epitaxial silicon formed above the second layer of epitaxial silicon, a trench isolation region that extends through at least the third layer of epitaxial silicon, the trench isolation region defining an active area, and at least one component of a semiconductor device formed in or above the third layer of epitaxial silicon within the active area.