The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7141453 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 28, 2006

Filed:

Sep. 14, 2004
Applicant:

Takehiko Murakami, Fuchu, JP;

Inventor:

Takehiko Murakami, Fuchu, JP;

Assignee:

Minami Co., Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

To make it possible to utilize both surfaces of a wafer, a wafer () is provided with a through hole () between upper and lower surfaces, an insulating layer () is formed in an inner surface of the through hole (), rewiring circuits () are formed on both the upper and lower surfaces, the rewiring circuits () are connected by a plating () applied on the insulating layer () within the through hole (), thermal stress relaxing posts () are formed on the rewiring circuits () by a conductive material such as a solder bumps () are formed on the thermal stress relaxing posts (), and the solder bump () or () is connected to a wiring circuit () of a printed wiring substrate ().


Find Patent Forward Citations

Murakami, Takehiko. (2006). Method of mounting wafer on printed wiring substrate (U.S. Patent No. 7141453). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7141453

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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