The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2006
Filed:
Jun. 28, 2002
Philip E. May, Palatine, IL (US);
Kent Donald Moat, Winfield, IL (US);
Raymond B. Essick, Iv, Glen Ellyn, IL (US);
Silviu Chiricescu, Chicago, IL (US);
Brian Geoffrey Lucas, Barrington, IL (US);
James M. Norris, Naperville, IL (US);
Michael Allen Schuette, Wilmette, IL (US);
Ali Saidi, Cambridge, MA (US);
Philip E. May, Palatine, IL (US);
Kent Donald Moat, Winfield, IL (US);
Raymond B. Essick, IV, Glen Ellyn, IL (US);
Silviu Chiricescu, Chicago, IL (US);
Brian Geoffrey Lucas, Barrington, IL (US);
James M. Norris, Naperville, IL (US);
Michael Allen Schuette, Wilmette, IL (US);
Ali Saidi, Cambridge, MA (US);
Motorola, inc., Schaumburg, IL (US);
Abstract
A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.