The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2006
Filed:
May. 31, 2005
Suman K. Banerjee, Chandler, AZ (US);
Enrique Ferrer, Miami, FL (US);
Olin L. Hartin, Chandler, AZ (US);
Radu M. Secareanu, Phoenix, AZ (US);
Suman K. Banerjee, Chandler, AZ (US);
Enrique Ferrer, Miami, FL (US);
Olin L. Hartin, Chandler, AZ (US);
Radu M. Secareanu, Phoenix, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A system-on chip (SOC) () and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks () and ESD protected pads (and). A VDD isolation pad () is connected to an N well ring () of the first noise sensitive circuit () to collect noise from the substrate () and isolate the circuit from the P well region (). A ground protected pad () is connected to an isolated P well () of a first noise sensitive circuit (). The ground pad () collects noise from the isolated P well () and sends it to ground. A dedicated ground isolation pad () is connected to a P well ring () of a second noise sensitive circuit (). The dedicated ground isolation pad () collects noise from the P well ring () and sends it to ground. The dedicated ground isolation pad () and the ground pad () collect noise that would normally propagate between the first and second noise sensitive circuits () and additional circuits that share the same substrate ().