The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2006

Filed:

Jun. 16, 2004
Applicant:

Akio Kitamura, Nagano, JP;

Inventor:

Akio Kitamura, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01);
U.S. Cl.
CPC ...
Abstract

A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.


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