Data synchronization hardware primitive in an embedded symmetrical multiprocessor computer

Abstract

An embedded symmetrical multiprocessor system includes arbitration logic that determines which central processing unit has access to shared memory. Upon grant of access, the memory address is stored in a memory address register. An address compare circuit compares the access address of any other central processing unit with this stored address. Upon a match, the arbitration logic stalls the second accessing central processing unit until expiration of a programmable number of wait states following the first access. These wait states give the first central processing unit enough time to determine the state of a lock variable and take control of an operation protected by the lock variable. The application boot code can determine how long the read-check-write operation requires and program that value into the wait-state generator.