The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7136318 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 14, 2006

Filed:

Jun. 21, 2005
Applicants:

Hirohisa Ohtsuki, Ashiya, JP;

Kazuo Itoh, Takatsuki, JP;

Katsuji Satomi, Osaka, JP;

Hironori Akamatsu, Hirakata, JP;

Inventors:

Hirohisa Ohtsuki, Ashiya, JP;

Kazuo Itoh, Takatsuki, JP;

Katsuji Satomi, Osaka, JP;

Hironori Akamatsu, Hirakata, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.


Find Patent Forward Citations

Ohtsuki, Hirohisa. (2006). Semiconductor memory device and circuit layout of dummy cell (U.S. Patent No. 7136318). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7136318

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