The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2006

Filed:

Dec. 10, 2003
Applicants:

Ching-nan Hsiao, Kao-Hsiung Hsien, TW;

Ying-cheng Chuang, Tao-Yuan Hsien, TW;

Chi-hui Lin, Nan-Tou Hsien, TW;

Inventors:

Ching-Nan Hsiao, Kao-Hsiung Hsien, TW;

Ying-Cheng Chuang, Tao-Yuan Hsien, TW;

Chi-Hui Lin, Nan-Tou Hsien, TW;

Assignee:

Nanya Technology Corp., Tao-Yuan Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.


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