The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Sep. 20, 2000
Shin-ichiro Tago, Kawasaki, JP;
Taizo Sato, Kawasaki, JP;
Yoshimasa Takebe, Kawasaki, JP;
Yasuhiro Yamazaki, Kawasaki, JP;
Teruhiko Kamigata, Kawasaki, JP;
Atsuhiro Suga, Kawasaki, JP;
Hiroshi Okano, Kawasaki, JP;
Hitoshi Yoda, Kawasaki, JP;
Shin-ichiro Tago, Kawasaki, JP;
Taizo Sato, Kawasaki, JP;
Yoshimasa Takebe, Kawasaki, JP;
Yasuhiro Yamazaki, Kawasaki, JP;
Teruhiko Kamigata, Kawasaki, JP;
Atsuhiro Suga, Kawasaki, JP;
Hiroshi Okano, Kawasaki, JP;
Hitoshi Yoda, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.