The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2006

Filed:

Apr. 05, 2002
Applicants:

Hiroshi Azakami, Ibaraki, JP;

Takaaki Konishi, Ibaraki, JP;

Hisaya Kato, Soraku-gun, JP;

Naoya Tokunaga, Moriguchi, JP;

Kazuaki Suzuki, Kyoto, JP;

Kazuya Ueda, Hirakata, JP;

Inventors:

Hiroshi Azakami, Ibaraki, JP;

Takaaki Konishi, Ibaraki, JP;

Hisaya Kato, Soraku-gun, JP;

Naoya Tokunaga, Moriguchi, JP;

Kazuaki Suzuki, Kyoto, JP;

Kazuya Ueda, Hirakata, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication sectionmultiplies a clock CK. A switchable sampling sectionselects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling sectionswitches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.


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