The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Aug. 06, 2004
Simon Siu-sing Chan, Saratoga, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Simon Siu-Sing Chan, Saratoga, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.