Circuit and method for faster frequency switching in a phase locked loop

Abstract

A PLL circuit arrangement includes a first frequency divider connected to a reference frequency source, a second frequency divider connected to the output of an oscillator controlled by the output of a loop filter, a phase/frequency detector that detects phase/frequency differences between the two divider outputs, a charge pump between the detector and the loop filter, a controller providing a changeable divider ratio to the first and/or second frequency divider, and a regulating signal generator that changes the output voltage of the loop filter applied to the oscillator in a controlled manner in response to a change of the divider ratio. The signal generator preferably has inputs connected to outputs of the controller and the frequency dividers, and an output connected to the charge pump and/or the loop filter to accelerate the recharging thereof in response to a change of the divider ratio.