The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2006

Filed:

Sep. 29, 2004
Applicants:

R. Thomas Cruz, Raleigh, NC (US);

Robert G. Gerowitz, Raleigh, NC (US);

Claudia M. Tartevet, Raleigh, NC (US);

Inventors:

R. Thomas Cruz, Raleigh, NC (US);

Robert G. Gerowitz, Raleigh, NC (US);

Claudia M. Tartevet, Raleigh, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An improved method and process is provided for verifying a digital logic design complies with certain manufacturing test rules or guidelines. A replacement is created for any portion of a design to make it usable by the manufacturing test tool set, without requiring the contents of that portion of the design to be implemented. The inputs and outputs of a portion of the design are examined for violations of the manufacturing test rules or guidelines. If there are no violations, the contents of this portion of the design are replaced with some basic contents which satisfy the manufacturing structure rules. The interconnections between logic blocks can then be tested using test generation tools to ensure the design does not violate manufacturing test rules or guidelines The compliance verification can thus be done much earlier in the design process than typically occurs.


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