The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2006

Filed:

Feb. 28, 2003
Applicants:

Robert W. Schoepflin, Port Jefferson, NY (US);

Richard E. Wahler, St. James, NY (US);

Ronald W. Streiber, Smithtown, NY (US);

John D. Virzi, Bayside, NY (US);

Donald D. Noviello, Smithtown, NY (US);

Inventors:

Robert W. Schoepflin, Port Jefferson, NY (US);

Richard E. Wahler, St. James, NY (US);

Ronald W. Streiber, Smithtown, NY (US);

John D. Virzi, Bayside, NY (US);

Donald D. Noviello, Smithtown, NY (US);

Assignee:

Standard Microsystems Corporation, Hauppauge, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.


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