The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Feb. 13, 2001
Kazuo Takagi, Tokyo, JP;
Naoya Henmi, Tokyo, JP;
Shinobu Sasaki, Tokyo, JP;
Kurenai Murakami, Tokyo, JP;
Motoo Nishihara, Tokyo, JP;
Yoshinori Rokugou, Tokyo, JP;
Kazuo Takagi, Tokyo, JP;
Naoya Henmi, Tokyo, JP;
Shinobu Sasaki, Tokyo, JP;
Kurenai Murakami, Tokyo, JP;
Motoo Nishihara, Tokyo, JP;
Yoshinori Rokugou, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.