The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Feb. 24, 2005
Dieter Draxelmayr, Villach, AT;
Franz Kuttner, St.-Ulrich, AT;
Christian Vogel, Graz, AT;
Infineon Technologies AG, Munich, DE;
Abstract
Circuit arrangement () for the delay adjustment of analog-to-digital converters (--N,) operating in a temporally offset manner, having at least two analog-to-digital converters (--N,) each having a signal path, which receive an analog signal (VI) present at an input () of the circuit arrangement () and in each case convert it into a digital intermediate signal (Z, . . . ZN), the analog-to-digital converters (--N,) in each case being clocked by clock signals (CLK, . . . CLKN) which have a predetermined time offset with respect to one another; having a logic circuit (), which interconnects the digital intermediate signals (Z, . . . ZN) for the purpose of generating a digital output signal (ZD) of the circuit arrangement (); it being possible to set the bandwidth of the signal paths of the analog-to-digital converters (--N,) in each case in such a way that a deviation of the clock signal (CLK, . . . CLKN) from the predetermined time offset for the respective analog-to-digital converter (--N,) is compensated for by a change in the bandwidth of at least signal path.