The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Dec. 14, 2004
Applicants:
Eric H. Voelkel, Ben Lomond, CA (US);
Robert M. Reinschmidt, Hollis, NH (US);
Greg J. Landry, Merrimack, NH (US);
Inventors:
Eric H. Voelkel, Ben Lomond, CA (US);
Robert M. Reinschmidt, Hollis, NH (US);
Greg J. Landry, Merrimack, NH (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.