The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2006

Filed:

Apr. 30, 2004
Applicants:

Vasisht Mantra Vadi, San Jose, CA (US);

David P. Schultz, San Jose, CA (US);

John D. Logue, Placerville, CA (US);

John Mcgrath, Cork, IE;

Anthony Collins, Dublin, IE;

F. Erich Goetting, Cupertino, CA (US);

Inventors:

Vasisht Mantra Vadi, San Jose, CA (US);

David P. Schultz, San Jose, CA (US);

John D. Logue, Placerville, CA (US);

John McGrath, Cork, IE;

Anthony Collins, Dublin, IE;

F. Erich Goetting, Cupertino, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.


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