The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2006

Filed:

Nov. 24, 2004
Applicants:

Mizuki Segawa, Osaka, JP;

Isao Miyanaga, Osaka, JP;

Toshiki Yabu, Osaka, JP;

Takashi Nakabayashi, Osaka, JP;

Takashi Uehara, Osaka, JP;

Kyoji Yamashita, Osaka, JP;

Takaaki Ukeda, Osaka, JP;

Masatoshi Arai, Osaka, JP;

Takayuki Yamada, Osaka, JP;

Michikazu Matsumoto, Osaka, JP;

Inventors:

Mizuki Segawa, Osaka, JP;

Isao Miyanaga, Osaka, JP;

Toshiki Yabu, Osaka, JP;

Takashi Nakabayashi, Osaka, JP;

Takashi Uehara, Osaka, JP;

Kyoji Yamashita, Osaka, JP;

Takaaki Ukeda, Osaka, JP;

Masatoshi Arai, Osaka, JP;

Takayuki Yamada, Osaka, JP;

Michikazu Matsumoto, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.


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