The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2006

Filed:

Feb. 16, 2006
Applicants:

Hajime Akiyama, Tokyo, JP;

Shinichi Izuo, Tokyo, JP;

Inventors:

Hajime Akiyama, Tokyo, JP;

Shinichi Izuo, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate () and an ntype semiconductor layer () are bonded to each other through a buried oxide film layer (). A first porous oxide film area () is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the ntype semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode () and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes ().


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