The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Sep. 08, 2003
Patrick James Mcguinness, Austin, TX (US);
Robert Lee Maziasz, Austin, TX (US);
Andrei Vladimirovitch Zinchenko, Moscow, RU;
Vladimir Pavlovich Rozenfeld, Moscow Region, RU;
Michael Viacheslavovich Golikov, Moscow, RU;
Alexander Mikhailovich Marchenko, Moscow, RU;
Patrick James McGuinness, Austin, TX (US);
Robert Lee Maziasz, Austin, TX (US);
Andrei Vladimirovitch Zinchenko, Moscow, RU;
Vladimir Pavlovich Rozenfeld, Moscow Region, RU;
Michael Viacheslavovich Golikov, Moscow, RU;
Alexander Mikhailovich Marchenko, Moscow, RU;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.