Low pin count, high-speed boundary scan testing

Abstract

In a method for testing a testable electronic device having a first and a second plurality of test a arrangements a first shift register () is used in parallel with a second shift register () to time-multiplex a first test vector () and a second test vector () into a number of smaller test vectors () for provision to the first and second plurality of test arrangements. By varying the size of the first shift register () and the second shift register () a trade-off between the number of pins of the electronic device to be contacted and the required test time can be made. The first shift register () may be coupled to a first buffer register () and second shift register () may be coupled to a second buffer register () for enhanced test data stability. First shift register () and second shift register () can be partitions of a larger shift register. The method can also be used in a reverse way by time-demultiplexing test result vectors into a single vector at the output side of the testable electronic device.