The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Nov. 17, 2003
Simon Charles Watt, Cambridge, GB;
Christopher Bentley Dornan, Cambridge, GB;
Luc Orion, Mouans Sartoux, FR;
Nicolas Chaussade, Mouans-Sartoux, FR;
Lionel Belnet, Villeneuve-Loubet, FR;
Stephane Eric Sebastien Brochier, Chateauneuf de Grasse, FR;
David Hennah Mansell, Usk, GB;
Michael Robert Nonweiler, Cambridge, GB;
Simon Charles Watt, Cambridge, GB;
Christopher Bentley Dornan, Cambridge, GB;
Luc Orion, Mouans Sartoux, FR;
Nicolas Chaussade, Mouans-Sartoux, FR;
Lionel Belnet, Villeneuve-Loubet, FR;
Stephane Eric Sebastien Brochier, Chateauneuf de Grasse, FR;
David Hennah Mansell, Usk, GB;
Michael Robert Nonweiler, Cambridge, GB;
Arm Limited, Cambridge, GB;
Abstract
An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.