The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7124232 B1

Expired

Date of Patent:

Oct. 17, 2006

Filed:

Feb. 19, 2004

Bus connection circuit and bus connection system having plural request queues, a bus interface portion outputting request signals, an arbiter performing arbitration of plural requests and a bus interface portion outputting a request signal indicating allocation of pre-fetch buffers corresponding to arbitrated requests

Applicants:

Yoshihiko Takeda, Kawasaki, JP;

Kentarou Yuasa, Kawasaki, JP;

Inventors:

Yoshihiko Takeda, Kawasaki, JP;

Kentarou Yuasa, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:

Staas & Halsey LLP

Primary Examiner:

Mark H Rinehart

Assistant Examiner:

Raymond N Phan

Int. Cl.

CPC ...

G06F 13/36 (2006.01);

U.S. Cl.

CPC ...

Abstract

A bus connection circuit is connected by a bus to a bridge circuit having a plurality of pre-fetch buffers to access memory. A plurality of request queues and a plurality of request signal outputs and grant signal inputs are provided in a single bus connection device. By means of the single bus connection device, a plurality of pre-fetch buffers of a bridge circuit can be utilized effectively, wasted read requests corresponding to retry responses from the bridge circuit can be decreased, and consequently wasted use of a PCI bus can be reduced.

Find Patent Forward Citations

Takeda, Yoshihiko. (2006). Bus connection circuit and bus connection system having plural request queues, a bus interface portion outputting request signals, an arbiter performing arbitration of plural requests and a bus interface portion outputting a request signal indicating allocation of pre-fetch buffers corresponding to arbitrated requests (U.S. Patent No. 7124232). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7124232

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