Methods and systems for reducing power-on failure of integrated circuits

Abstract

Methods and systems for protecting integrated circuits from power-on sequence currents and for biasing transistors in paths susceptible to power-on sequence damage are provided. The system includes a plurality of protection circuits coupled between a first circuit input and a second circuit input. Each protection circuit includes a switch and a voltage sensors. When the voltage amplitude of a first voltage source coupled to the protection circuit exceeds a first threshold and the voltage amplitude of a second voltage source coupled to the protection circuit is below a second threshold, the switch is closed, coupling the first circuit input to the second circuit input. When the voltage amplitude of the first voltage source exceeds the first threshold and the voltage amplitude of the second voltage source exceeds the second threshold, the switch is open, decoupling the first circuit input from the second circuit input.